In the back-end-of-line metallization layers formed during fabrication of integrated circuits, copper is typically used for electrical interconnections. Conductive copper features using a damascene, dual-damascene or via process begin with etching patterns in order to create open trenches, vias, or other cavities where the copper features will be inlayed, in an underlying substrate, such as silicon, silicon oxide, or a low-dielectric-constant (low k dielectric) insulating layer. A barrier/adhesion layer is coated over the etched and patterned substrate, and copper metal is typically deposited on the substrate to overfill the open cavities. A thermal treatment can be performed to stabilize the grain structure of the metal. A chemical-mechanical planarization (CMP) process may then be applied to remove the unwanted metal overburden that extends above the top surface of the substrate. The copper metal, for example, that remains in the substrate becomes the patterned copper conductor for circuits of the integrated circuit.
Successive layers of insulator material and copper can build a multilayered interconnection structure. One or more CMP processes remove the overburden copper and the barrier layer in a planar and uniform manner, ideally stopping at each substrate surface. However, over the patterned copper conductor features, the CMP process may introduce some dishing in larger copper features that have a larger surface area, because the copper is often softer than the dielectric layer, which may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, diamond-like-carbon or the like. The larger the width of the cavity that has been filled with copper metal, for example, the larger the observed dishing during the polishing.
As shown in FIG. 1, dishing 100 is a concave dip defect in the top surface 102 of a metal feature 104, and the dishing 100 becomes more pronounced in relation to the width 106 of the metal feature 104, especially for large damascene features 104 with widths 106 greater than 4 microns (4μ). Typically, the dishing 100 increases with increasing width of the conductive feature 106. The fabrication process begins with a barrier 108 and seed layer 110 deposited in cavities 112 (trenches or vias) of an insulator or semiconductive substrate 114.
The cavities 112 may then be plated with metal to overfill the cavity and cover the surface surrounding the cavity 112, which may be referred to as the “field” to distinguish this surface area from the cavity itself. In one example, for copper deposited from an appropriate conventional copper additive plating bath, a field metal thickness Tf 116 and a cavity metal thickness Tc 118 are similar in thickness. The field metal thickness Tf 116 is typically greater than the overburden metal thickness To 120 over the cavities 112. After thermal treatment to partially stabilize the grain structure of the metal, the grain size of the metal field metal thickness Tf 116 is similar to the grain size of the cavity metal thickness Tc 118.
A planarization process, such as a CMP process (illustrated by dashed arrow 122) stops at the barrier layer 108 over the field after polishing with a deformable pad. On account of the similar grain size between the field metal Tf 116 and the cavity metal Tc 118, the removal rates of the field metal Tf 116 and the cavity metal Tc 118 are quite similar with a given etchant or polishing slurry.
Then, after removal of the barrier layer 108, the substrate 114 has metal features 104 with the excessive dishing 100. As an example, for a one-micron deep cavity with a width 106 of 4-10 microns, the dishing 100 may vary between 10-50 nm. For larger cavities (in diameter, length, width, etc.) the dishing 100 may readily exceed 30 nm.
When two metal features 104 & 104′ are joined to make a bonded feature 124, such as a conductive connection (with each other) for large pad bonding, the dishing 100 on both surfaces creates an unwanted space 126 between the surfaces of the two metal features 104 & 104′. The unwanted space 126 may be continuous or discontinuous along the width of the cavities in the bonded metal features 104 and 104′. In some examples, the length of the unwanted cavity (dishing) 126 may comprise a dip magnitude that is 5-60% of the width 106 of the width of the metal feature 104 in the dielectric cavity. The dishing 100 and spaces 126 are unacceptable defects in bonded damascene features, and such large defects are a major source of failure in bonded devices.
FIG. 2 shows an example conventional approach for creating bonded features, when dishing is present. In diagram 200, a substrate with a conductive feature with excessive dishing and dielectric erosion has a pad opening dimension P1. In diagram 202, the substrate has been coated with one or more layers of dielectric material. In diagram 204, the dielectric has been planarized. In diagram 206, lithographic patterning is formed atop the planarized dielectric. In diagram 208, single or dual damascene etching processes form a second pad opening P2, where P2 is less than P1. In diagram 210, a barrier layer and seed layer (not shown) have been placed, and metal deposition has occurred. The plated metal is annealed to partially stabilize the grains of the coated metal. In diagram 212, metal planarization is performed. In diagram 214, two damascene features are bonded after surface preparation and substrate assembly.
The example conventional approach of FIG. 2 has some drawbacks and limitations. First, more than seven additional steps are needed to solve the initial dishing of the large damascene features after CMP. Secondly, the second pad opening P2 in diagram 212 is always smaller than the first pad opening P1. Thirdly, this technique, used in some instances when creating direct bond interconnect (DBI®) hybrid bonding layers, can be relatively expensive. Fourth, the example conventional approach results in a loss of wiring freedom or design flexibility in which coplanar large metal and small metal features are components of the bonding surface.